100 Power Tips for FPGA Designers by Evgeni Stavinov

By Evgeni Stavinov

This e-book is a set of brief articles on a variety of points of FPGA layout: synthesis, simulation, porting ASIC designs, floorplanning and timing closure, layout methodologies, functionality, zone and gear optimizations, RTL coding, IP center choice, and so forth. The publication is meant for method architects, layout engineers, and scholars who are looking to enhance their FPGA layout abilities. either amateur and pro good judgment and engineers can locate bits of worthy info. This ebook is written through a practising FPGA common sense dressmaker, and encompasses a lot of illustrations, code examples, and scripts. instead of delivering details appropriate to all FPGA proprietors, this publication variation specializes in Xilinx Virtex-6 and Spartan-6 FPGA households. Code examples are written in Verilog HDL. All code examples, scripts, and initiatives supplied within the e-book can be found on accompanying web site: http://outputlogic.com/100_fpga_power_tips

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Not only can a skew impact the achievable clock speed of a circuit but, in the worst case, it can cause incorrect operation of the circuit. Low-skew clock routing can also be used for non-clock signals, such as reset or high-fanout controls. Xilinx FPGA die is divided into several clock regions as is illustrated in the following figure. Figure 1: Eight clock regions Virtex-6 FPGAs have between six to 18 clock regions, depending on the device. There are three types of clocks: global, which can drive synchronous logic on the entire die; regional, which can drive logic in specific and adjacent regions; and IO, which can serve the logic specific to that IO.

Verilog-95 had been evolving, and in -2001 IEEE released another standard, 1364-2001, also known as Verilog-2001. It contained a lot of extensions that cover the shortcomings of the original standard, and introduced several new language features. In 2005 IEEE published a 1364-2005 standard, known as Verilog 2005. It included several specification corrections and clarifications, and a few new language features. IEEE published several SystemVerilog standards. The latest one is 1800-2009, which was published in 2009.

It also ensures a glitch-free operation when the input clock selection is changed. Clock multiplexing requires careful timing constraints of all paths from an input to an output clock of the multiplexer. Detecting clock absence One method of detecting clock absence is to use an oversampling technique by another higher speed clock. The disadvantage of this method is the availability of another clock. An alternative method is to use the locked output from Xilinx MMCM primitive, as shown in the following figure.

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