Alpha AXP Architecture Reference Manual by Richard L. Sites, Richard T. Witek

By Richard L. Sites, Richard T. Witek

Alpha AXP structure Reference handbook

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Fa A floating-point register operand in the Ra field of the instruction. Fb A floating-point register operand in the Rb field of the instruction. Fc A floating-point register operand in the Re field of the instruction. Instruction Formats (I) 3-3 Table 3-2: Operand Value Notation Notation Meaning Rav The value of the Ra operand. This is the contents of register Ra. Rbv The value of the Rb operand. This could be the contents of register Rb, or a zero-extended 8-bit literal in the case of an Operate format instruction.

2. 5 Processor Cycle Counter (PCC) Register The PCC register consists of two 32-bit fields. The low-order 32 bits (PCC<31:0>) are an unsigned, wrapping counter, PCC_CNT. The high-order 32 bits (PCC<63:32>), PCC_OFF, are operating system dependent in their implementation. PCC_CNT is the base clock register for measuring time intervals, and is suitable for timing intervals on the order of nanoseconds. 16. The cycle counter frequency is the number of times the processor cycle counter gets incremented per second.

The literal is interpreted as a positive integer Instruction Formats (I) 3-11 between 0 and 255 and is zero-extended to 64 bits. Symbolically, the integer Rbv operand is formed as follows: IF inst<12> EQ 1 THEN Rbv <- ZEXT(inst<20:13>) ELSE IF inst<20:16> EQ 31 THEN Rbv «- 0 ELSE Rbv *— Rb END END The Re field specifies a destination operand. 4 Floating-Point Operate Instruction Format The Floating-point Operate format is used for instructions that perform floatingpoint register to floating-point register operations.

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