Architecture of High Performance Computers Volume II: Array by R. N. & Topham, N. P. Ibbett

By R. N. & Topham, N. P. Ibbett

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Extra resources for Architecture of High Performance Computers Volume II: Array processors and multiprocessor systems

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The se lee ted input may be eomplemented before addition, enabling subtraetion and logical inversion operations to be implemented. The earry-in to the single-bit adder may eome from one of two sourees, either the loeal earry register or the earryout of the Eastern neighbour, depending on the operating mode of the array. This ehoice permits the DAP to perform word-arithmetie in two quite distinet ways, either bit-serial (word-parallel) or bit-parallel (wordserial). 7. The normal mode of arithmetie in the DAP is bit-serial word-parallel.

Interconnection structures consist of active switching nodes connected by passive links. They can be represented as graph structures in which the active switching nodes form the ver ti ces and the links between them form the edges. In order to implement specific routing functions a set of control signals must be generated for every active component. These control signals could be generated by a single control unit, using information about all the connections requiredj this is known as centralised control.

The operating mode of interconnection structures for multiprocessor systems is normally asynchronous, since the initiation of data movement is controlled by independent instructions in each processor. Interconnection structures consist of active switching nodes connected by passive links. They can be represented as graph structures in which the active switching nodes form the ver ti ces and the links between them form the edges. In order to implement specific routing functions a set of control signals must be generated for every active component.

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