Automatic Logic Synthesis Techniques for Digital Systems by Martyn D. Edwards

By Martyn D. Edwards

Fresh advances in microelectronics expertise have resulted in the expanding usage of built-in circuit parts in almost all sectors of society. One specific part is the Application-Specific built-in Circuit, ASIC, that is hired in such various items as washing machines, automobile engines and mainframe pcs. The winning use of ASICs in items is because of the exploitation of computer-aided layout instruments, specially computerized synthesis instruments, which lessen time and price. This booklet stories the state of the art in common sense synthesis suggestions, that have lately been built for ASIC parts. every one bankruptcy ends with entire study references.

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B a. 6 Simple n-channel and p-channel transistor networks is detennined by: (1) The network Fp provides transmission paths for all combinations of the input signals X, where F(X) = logic 1 ; that is Fp =F. (2) The network Fn provides transmission paths for all combinations of the input signals X, where F(X) = logic 0 ; that is Fn = F'. 7(b). b). The network structures for Fp and Fn are duals of each other - each variable in Fp is replaced by its complement in Fn and the AND and OR operations are interchanged.

A'c ------. b d . 12 K-map for f4 The procedure for identifying all the prime implicants of a function using a K-map may be summarised as follows: Encircle the largest possible groupings of adjacent cells such that each cell containing a 1 is enclosed in at least one group. Each such group is a prime implicant of the function. 12(b). 40) 34 Automatic Logic Synthesis Techniques for Digital Systems Identification of the essential prime implicants is straightforward. Any cell that is in only one grouping can be easily recognised - such a grouping must be an essential prime implicant.

Egan and Liu (1984) define a simpler notion of folding, known as bipartite folding. Although this problem is also NP-complete, they describe an efficient 'branch-and-bound' algorithm to fmd the optimal bipartite folding of a PLA. A bipartite folding is one where all the column 'breaks' occur in the same row of a PLA. The authors show that an optimal bipartite fold approaches the size of an optimal simple PLA fold; hence, it is a worthwhile exercise to find such folds. A brute force approach to PLA folding produces an algorithm computation time which is proportional to 2n, where n is the sum of the number of inputs and outputs of a PLA.

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